A 58 ns 4 Mb CMOS DRAM with an effective one-shot gate address buffer

A 4-Mb CMOS dynamic RAM (DRAM) with an effective one-shot gate address buffer has been fabricated. The buffer greatly reduces row address hold time, which gives a fast RAS (row-address strobe) access time of 58 ns. The RAM also implements a novel standby current limitation circuit, which saves the current in the first stage of the buffer even with the TTL-level input voltage. The memory cell has a stacked capacitor. The RAM measures 6.84 mm*14.95 mm and is housed in a 350-mil small-outline J-leaded (SOJ) package and a 400-mil zig-zag in-line package (ZIP).<
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