Modeling and characterization of 0.35 μm CMOS coreless transformer for gate drivers

In this paper, a monolithic solution based on integrated coreless transformer (ICT) for galvanic isolation and power transfer application is demonstrated. First, the characterization of ICTs is investigated by a set of five devices with stacked topology but different geometrical parameters fabricated in a 0.35 μm H35B4M3 CMOS technology from AMS. Second, the behavior of these ICTs is also predicted by electromagnetic (EM) simulation in Ansoft HFSS and analyzed by their equivalent electrical model. The measured results have shown a peak of voltage gain of −3 dB with the design of 300 μm of diameter while charging with the input capacitance of 900 fF of the demodulated circuit. Finally, an integrated gate driver is also fabricated using the optimal design of ICT, achieving a compact area of 0.72 mm
²
and offers 1.8 kV of isolation. The experimental results of this gate driver have validated the use of isolated signal and energy transfer by on-chip transformer for both high side and low side applications.