VLSI implementation of a high speed second order sigma-delta modulator with high-performance integrators

Oversampling analog-to-digital converters based on second-order sigma-delta (/spl Sigma//spl Delta/) modulation are attractive for VLSI implementation because they are tolerant of circuit nonidealities and component mismatch. This paper compares a high speed second-order /spl Sigma//spl Delta/ modulator to several alternative modulator architectures in the context of large bandwidth signal acquisition. Design details are presented for 0.5-/spl mu/m CMOS implementation. The experimental modulator is a fully differential circuit that operates from a /spl plusmn/3 V power supply and does not require the use of precision sample-and-hold circuitry. With an input bandwidth of 20 MHz and a clock rate of 160 MHz, the modulator reaches 26 dB signal-to-quantization noise (power) ratio (SQNR) using spectra simulation. All the elements of this design have implemented using switched-capacitor circuit techniques. Two identical noninverting parasitics-insensitive lossless switch capacitor sharing integrators have been used in order to achieve a large bandwidth and a linear integration.