1-D discrete time CNN with multiplexed template hardware

While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S/sup 2/I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architecture.