A 0.6/1.2-V 14.1-mW 96.8GHz-to-108.5GHz transformer-based PLL with embedded phase shifter in 65-nm CMOS

A low-voltage and low-power 96.8-108.5 GHz transformer-based PLL is implemented in a 65 nm CMOS technology. Consuming only 14.1 mW from 0.6 V/1.2 V supply, the PLL measures phase noise of -84 dBc/Hz at 100-kHz offset and -88 dBc/Hz at 1-MHz offset from a 99.4 GHz carrier while occupying a core chip area of 0.39 mm². Moreover, with an embedded phase shifter, the PLL output phase can be shifted by 360° range with an average resolution of 3.9° and amplitude variation less than ±0.1 dB.