A compact 24–54 GHz CMOS band-pass distributed amplifier for high fractional bandwidth signal amplification

This paper describes a compact 24-54 GHz two-stage band-pass distributed amplifier (BPDA) utilizing dual mirror-symmetric Norton transformations to reduce inductor component values allowing an area-efficient layout. The BPDA, implemented in a 40nm CMOS process, occupies an active area of 0.15mm
²
, has a 77% fractional-bandwidth, an overall gain of 7dB, a minimum in-band IIP3 of 11dBm, inband noise-figure less than 6.2dB while consuming 34mA from a 1V supply.