Mixed FBB and RBB low leakage technique for high durable CMOS circuit

CMOS logic circuit is extensively used for designing low power Very Large Scale Integration (VLSI). Reducing the dimension of CMOS in a nanometer range, functionality and efficiency can be increased, but as a result we have to compromise with circuit level leakage. As circuit level leakage also known as leakage current is currently one of the major concernments to the VLSI designers. These Leakage currents are generated due to different types of leakage current components such as Weak inversion current, Drain-induced barrier lowering (DIBL), Gate-induced drain leakage and Oxide leakage tunneling. However, there are wide ranges of method that are already available to reduce these leakages, but all of them have their own tradeoffs. In this paper we propose a novel technique by integrating the idea of Forward Back Bias (FBB) and Reverse Back Bias (RBB) which reduces leakage extensively than sleepy stack, stacked sleep, variable body biasing and dual sleep. Furthermore, RBB and FBB are yielded with forced stacked transistors where RBB is accountable for nullifying the leakage and FBB is responsible for offsetting the delay penalty. The proposed method is scrutinized under 22nm to 65nm feature size, and it has come out that these novel schemes are especially very effective for designing the future low-voltage, low-power CMOS VLSI's [1]. Therefore, the main principle of this technique is to trim down leakages, but it has an obvious delay constraint that is considered as a tradeoff in this particular case.