A 65nm CMOS 140 GHz 27.3 dBm EIRP transmit array with membrane antenna for highly scalable multi-chip phase arrays

This paper presents a scalable transmit phase array operating at 140 GHz which employs a local PLL reference generation system. Unlike traditional CMOS phase arrays, this enables the array to be formed over multiple chips while avoiding the challenges of distributing mm-wave signals between them. The prototype chip consumes 131 mW of power and occupies 1.95 mm
²
of chip area when implemented in 65 nm CMOS technology.