Advanced soft fail characterization methodology for sub-28nm nanoscale SRAM yield improvement

CMOS device miniaturization and the rapidly growing demand for mobile or power-aware systems have resulted in an urgent need to lower down power supply voltage (Vdd). However, soft fails at low Vdd in SRAM Array become a major yield limiter due to process variation and VT mismatch. This paper describes an advanced characterization flow on soft fails with the combination of applying fail-specified functional memory patterns, circuit analysis and advanced PFA techniques. The flow was successfully applied in soft fail characterization for sub-28nm SRAM yield improvement.