Improvement of CMOS latch-up in bootstrapping circuit application

This work presents a design guideline for free latch-up in the CMOS inverter caused by shifting time waveform for various device sizes which is demonstrated by 2D TCAD simulations. The design window for improving the CMOS latch-up is investigated by increasing distance anode to cathode of parasitic silicon-controlled-rectifier (SCR) or source to bulk of NMOS.