Faster Translated Binary Execution on Mobile System through Virtualization

One of the challenges of the binary translation on virtual machine(VM) is to make a mapping from registers in emulated architecture to registers in the target architecture. The efficiency on the emulated architecture is best translated into efficiency on the target machine if target instructions also operated on register operands. However, conventional binary translators of popular VMs do not take into account instruction dependency among two or more basic blocks. This results in performance degradation due to inter-translation block dependency. Because binary translation makes use of 1 or 2 registers repeatedly for the majority of translation blocks. The translation block corresponds to a guest(emulated) instruction, which in turn the amount of work is not large. Even though there are no dependencies between translation blocks, false dependencies are generated by the repeated use of the same register usage order. In order to resolve the problem, we propose a novel approach maintaining two different register allocation orders, applying them alternatively. We call this as alternative register allocation in this paper. The experimental results show up to 26.3% better performance to conventional method.