Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs

We show that planar Fully Depleted Silicon-On-Insulator (FDSOI) technology allows improving the threshold voltage V
T
variability of CMOS devices in comparison to standard bulk CMOS devices. Moreover, integrated on Ultra-Thin Body and Buried oxide (UTBB), it enables the use of standard power management techniques (Reverse or Forward Back Biasing) without V
T
variability penalty. Drain current I
D
mismatch variations (σ
ID
) are found to be correlated with both threshold voltage (V
T
) and ON-state resistance (R
ON
) fluctuations. Additionally, the impact of R
ON
and V
T
variations is significantly reduced by their advantageous correlation, while σ
ΔVT
remains the major σ
ID
contributor. Finally, we demonstrate that SiGe channel could be used to improve global V
T
variability of short channel pMOS devices in addition to enhanced performances.