32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation

A 2×VDD Output Buffer using PVTL compensation is proposed in this paper. Beside the PVT compensation, a Leakage compensation circuit is employed. With the proposed Leakage compensation circuit, the SR (slew rate) and data rate are improved by 32% and 27%, respectively, for VDDIO = 1.8 V at the worst case. Moreover, the reliability problem caused by the unstable voltage, gate oxide overstress and hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The core area is 0.425 mm × 0.0563 mm. The SR is simulated to be 1.3-3.0 V/ns. The data rate is simulated to be 454, 370, and 500 MHz for VDDIO = 1.8, 1.2, and 1.0 V, respectively.