Generic SDR architecture: Vendor independent implementation

This paper describes a flexible hardware and software architecture that is simple, works with almost all Software Defined Radios (SDR) in market today and is vendor independent in its implementation. Usually, an engineer targets a particular platform which needs considerable time and manpower for process of design and development. The proposed architecture can be applied almost exclusively to the FPGAs, using a soft processor core to perform basic software functions as well as the main role of digital signal processing. The memory map to other logic modules and external peripherals as well as a boot-loader for loading the software image have been designed. A FIFO based component interface has been designed to maintain communication between modules and external devices as well as a data logger module for debug purposes. Since the entire hardware-software ecosystem is built on a single FPGA using Register Transfer Level (RTL) coding, it can freely be used on any FPGA family by any FPGA vendor with minor modifications. This allows us to build powerful SDR systems even using basic FPGA kits, an RF-frontend and an Analog-to-Digital (ADC) module. A survey of open source processor cores is conducted to estimate resource usage and complexity on an FPGA. This can be used to select an FPGA and a processor core such that the entire system can run on a single FPGA. This architecture is implemented on an existing SDR platform and all features are successfully validated on the hardware. Data logged from this system while running a sample signal processing implementation, was tested in Matlab and was shown to have correct time and frequency domain signals at various points in the signal processing chain.