A network-on-chip for radiation tolerant, multi-core FPGA systems

This paper describes research efforts to mitigate weaknesses in a TMR+spares radiation tolerant SRAM-based FPGA computer system. An existing 9-tile Microblaze architecture is reviewed and the desired improvements of fault-mitigated routing, fault location determination and performance enhancement via runtime-configurable hardware accelerators are discussed. Hamming encoding is proposed as a method for protecting the routing resources from radiation-induced single event upsets and as feedback to the computer's configuration control system to distinguish faults occurring in routing from those occurring within partially reconfigurable processing tiles. This is important as the recovery operation for each of these conditions is unique. Without the ability to distinguish routing faults from tile faults, routing faults are aliased as tile faults and unnecessary tile repair steps are taken. In addition to the protected routing with configuration control feedback, architecture for implementing TMR, processor-peripheral hardware accelerators is introduced.