FPGA based extension to the multichannel pixel readout ASIC

This paper presents the realization of the FPGA extension to the multichannel, pixel readout ASIC called VIPIC, designed in the collaboration between Fermi National Laboratory and AGH UST for X-ray Photon Correlation Spectroscopy (XPCS) experiments at BNL (Brookhaven National Laboratory). The FPGA was proposed to extend the digital backend of the chip and supply it with 32-bit long counters allowing effective operation in imaging mode, working in continuous readout mode at 50 MHz together with intelligent control of supporting digital lines, communication verification, the data compression and providing higher abstraction level for other systems communicating with it. The paper presents a new approach of building such systems including tools and methods allowing implementation of high-speed data processing without deep knowledge of FPGA structure or Hardware Description Language (HDL) experience. The advantage of LabVIEW™ graphical system design for both FPGA and Real-Time OS programming is presented for building testing setup including automatic procedures like threshold scans and automatic correction with user-defined algorithms.