Thermal stresses around void in Through Silicon Via in 3D SiP

Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using FEM (Finite Element Method). In case of the condition of device operation, equivalent stress around void inside Cu TSV was estimated at around 100 MPa. It showed the low possibility for low cycle fatigue of Cu TSV under device operation because that the stress was lower than yield stress of copper, 210MPa. Maximum principal stress of Si was estimated around 100 MPa. It was lower than bending stress of Si. In case of the condition of reflow process, the equivalent stress of TSV with void was higher than yield stress of Cu. However temperature elevation due to reflow process was once or twice during the process. It showed the low possibility for fracture by low cycle fatigue under reflow process. In case without void, maximum principal stress of Si was estimated around 400 MPa. It was almost similar to the bending strength of Si. Stress concentrations were occurred at parts of corner and interface of materials. It has possibility that singular stress field was formed at the parts, and we should discuss fracture induced by singular stress field.