Phase Based and Application Based Dynamic Encoding Scheme for Multi-level Cell STT-RAM

The emerging Spin Torque Transfer memory (STT-RAM) appeared to be a promising candidate for future on-chip caches because of its high storage density, zero leakage power consumption, long endurance, high access speed etc. However, before the STT-RAM can be deployed in on-chip caches, there is one critical issue that has to be solved: the high write current of STT-RAM, which results in high dynamic power consumption. Each cell of multi-level cell STT-RAM (MLC STT-RAM) has four resistance states which can present the four 2-bit logical value pairs (00, 01, 10 and 11). We find that the proportion of the 2-bit logical value pairs written to L2 Cache changes with time and applications. Since the four resistance states have different write energies, we therefore propose schemes to map the four resistance states to the four 2-bit logical value pairs dynamically according to their proportions. The resistance state which has lower write energy can represent the 2-bit logical value pair which appears more frequently. In this paper, we propose phase based dynamic encoding policy (PBDE) and application based dynamic encoding policy (ABDE). The PBDE divides an entire process into many phases, and each phase chooses its best encoding policy to minimize power consumption. The ABDE chooses the best encoding scheme for cache blocks according to application types. Our evaluations show that PBDE and ABDE can achieve 2.7% and 4.5% write energy reduction over STT-RAM based caches respectively.