A design of charge pump phase locked loop for DAC

Low jitter charge pump phase locked loop (CPPLL) is designed for 12 bit digital to analog converter (DAC) in this paper. It's reference frequency is from 3M to 100M. The design uses the model of SMIC 0.13um mixed-signal process, its power supply is 1.2V, the simulating tools are cadence's Spectre and Hspice. This paper mainly includes circuit design of Phase Frequency Detector (PFD), Charge Pump (CP), Low-Pass Filter (LPF) and Voltage Control Oscillator (VCO). The simulation result is proved that the CPPLL satisfies the design request. Its locking time is greater than 5us, and smaller than 23us. When the reference clock is 100MHz, VCO frequency is 400MHz, its jitter time (root-mean-square) is 4.314ps.