The first stage design of a SHA-less 12-bit 200-Ms/s pipeline ADC in 130-nm CMOS

A first stage of a SHA-less 12-bit 200 MSps pipeline analog-to-digital converter (ADC) is designed in this paper. A high speed and high precision comparator is designed in order to reduce the transmission delay of the comparator. RC network of the multiplying digital-to-analog converter (MDAC) and Sub-ADC should be strict matched in order to reduce the sampling errors between the two path. The prototype circuit, implemented in SMIC 130nm 1P5M CMOS process under 1.2V power supply with a 94MHz input signal and 200MHz sampling clock, demonstrates a SNDR of 82.7dB, a SNR of 72.6dB, and a ENOB of 11.83 bit.