Performance and Evaluation of Loopback Virtual Channel Router with Heterogeneous Router for On-Chip Network

Network on Chip (NOC) is a important communication infrastructure for system on chips (SOC). Router is most important parameter of the NOC. Area and performance both play a vital role in network on chip (NOC) architecture. In this paper we implement the loop back virtual channel router by comparing the look - ahead speculative virtual channel and baseline router architecture. In this implemented loopback virtual channel router, if there is a request to a busy buffer, the router will store incoming packet in any other suitable free buffer in the router. This router will be complete a look-back operation before entering a wait state. Goal of this architecture is to achieve better performance for area and latency with the help of various simulations. The architecture will be developed and simulated using hardware description language (HDL) and synthesize on the FPGA kit using Xilinx ISE.