A 1 GHz image-rejection down-converter in 0.8 /spl mu/m CMOS technology

A 1 GHz image-rejection down-converter implemented in a 0.8 /spl mu/m CMOS process is presented. The down-converter consists of a quadrature generator and mixers. The proposed architecture has an image-rejection characteristic that are insensitive to the phase error of the higher frequency first local oscillator (LO). The down-converter has an image-rejection characteristic of 29.3 dB under 2/spl deg/ phase error of the lower frequency second LO. The down-converter dissipates 108 mW at a 3.3 V supply.