A Self-Triggered Column-Level ADC for CMOS Pixel Sensors in High Energy Physics

CMOS pixel sensors (CPS) for the future linear collider vertex detector (VXD) have strict requirements on their analog readout electronics, particularly on the analog-to-digital converter (ADC). This paper presents a low-power and small-area 4-bit column-level ADC for the CMOS pixel sensor, foreseen to equip the outer layers of the VXD. The ADC employs a self-triggered timing and completes the conversion by performing a multi-bit/step approximation. Accounting the fact that in the outer layers, the hit density is in the order of a few per thousand, this ADC is designed to operate in two modes: active mode and inactive mode. The average energy and total capacitance are significantly reduced by a power-gating control and a switching network, respectively. The ADC is fabricated in a
${\hbox{0.35}}~\mu\hbox{m}$
CMOS process with a pixel pitch of
${\hbox{35}}~\mu\hbox{m} $
. It is implemented with 48 columns in a sensor prototype. Each column ADC occupies an area of
$ 35\times 545~\mu\hbox{m}^2$
. The measured temporal noise and fixed pattern noise (FPN) are 0.94  and 0.30 mV, respectively. The power consumption, at a 3-V supply and 6.25-MS/s sampling rate, equals to
${\hbox{486}}~\mu\hbox{W}$
in its inactive mode, which is by far the most frequent. This value rises to
${\hbox{714}}~\mu\hbox{W}$
in case of the active mode. These computations indicate an average power consumption of each column in the order of
${\hbox{487}}~\mu\hbox{W}$
, assuming a typical occupancy of
$ \sim {\hbox{0.5}}\%$
in the whole sensor. Its DNL and INL are 0.49/-0.28 and 0.29/-0.20 least significant bit, respectively.