On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices

We investigate the operation and performance of planar SiGe/Si and In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the hetero-junction and the metallurgical junction is beneficial to improve I_ON but for the considered devices the ON-current at V_DD=0.5V and I_oFF=1pA/μm hardly exceeds 1μA/μm. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.