Improving CMOS open defect coverage using hazard activated tests

Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic values through the charging of the floating node by small leakage currents in the circuit, although with large delays. It is well known that many open defects are not covered by commonly employed TDF launch on capture (LOC) scan delay tests; the coverage of specially generated transistor stuck-open tests published in the literature is only modestly better. It is commonly assumed that such undetected open faults are benign because the circuit states needed to activate them cannot be reached in normal functional operation. However, traditional test generation only considers final “steady state” signal values and ignores transients. In practice CMOS circuits experience many more transient states from the large number of hazards that occur during switching transitions. Many undetected open defects can be activated by such hazards during normal operation and cause a functional error. Such open faults must be detected by tests targeting low DPPMs. In this paper we present an ATPG based delay test methodology to target a key class of such hazard activated open faults that are not detected by traditional stuck open tests. Through detailed SPICE simulations, we show that the detected open defects can in fact be activated by such tests and therefore result in erroneous outputs in normal functional operation.