Multi-core SoC architecture exploration with radar digital system based on dataflow graph method

This article outlines a fully complete process in the term of exploration and evaluation about the multi-core SoC architecture with target radar algorithms computing on it. As powerful radar system is in need and SoC technology is widely used in radar field, architecture considers not only speed of processing units but also large data throughput of multi-channels. This work focuses on the architecture exploration of radar signal processing system by using dataflow graph method. After creating dataflow graphs and accurate architecture models in SystemC-based simulation platform at system level, dataflow graph mapping strategy can be implemented into the models. Static computation and dynamic simulation with precise simulation results are used to analyze the mapping strategy and architecture. The one which can best fulfill the demand of target application at a lower cost is the purpose. A specific optional SoC architecture and several algorithms are used as an example to illustrate this complete process.