A 12 Gb/s standard cell based ECL 4:1 serializer with asynchronous parallel interface

This paper presents an implementation of an high speed, double data rate, fully differential ECL (Emitter Coupled Logic) serializer. For this purpose, a novel robust ECL standard cell library was developed. The design is composed using a digital design flow, described in Hardware Description Language (HDL), and transfered manually in the analog design environment. The serializer has a parallel 4-bit FIFO interface, and can either communicate synchronously or asynchronously using the 2-phase bundled-data protocol. The FIFO consists of 4 stages and is realized as a micropipeline with a Muller pipeline as backbone. The entire circuit is developed in a 0.25 μm SiGe BiCMOS process and operates nominally at 3.3V. Simulation results show a maximal data rate of 12 Gb/s while drawing a current of 96.64mA only. Finally, the design and its components are compared to other SiGe-based published implementations.