Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs

In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si
_0.5
Ge
_0.5
source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, L
_g
, and ON-current, I
_ON
, which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.