A low-power PLA for a signal processor

A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70 degrees C indicate that the circuit works as expected in a range extending to at least 3.5 V.<
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