4-6 Bit Variable Resolution ADC

A low power variable resolution analog-to-digital converter (ADC) architecture has been proposed in a 45-nm CMOS technology. The design uses only 6 comparators for achieving the required conversion and thus saves huge amount of area in comparison to conventional flash ADC (which requires 2
ⁿ
comparators for same bits). The proposed ADC when designed for 4 - 6 bits, exhibit a SNR of 35.9 dB and SNDR of 35.4 dB and achieves a maximum speed of 1.4 GS/s. The ADC dissipates 80 μW, 96 μW and 1.15 mW power for 4, 5 and 6 bits respectively.