Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes

We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.