Bias Temperature Instability analysis of FinFET based SRAM cells

Bias Temperature Instability (BTI) is posing a major reliability challenge for today's and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write Trip Point (WTP); while the aspects investigated include BTI impact dependence on the supply voltage, cell strength, and design styles (6 versus 8 Transistors cell). A comparison between FinFET and planar CMOS based SRAM cells degradation is also covered. The simulation performed on FinFET based cells for 10
⁸
seconds of operation under nominal V
dd
show that Read SNM degradation is 16.72%, which is 1.17× faster than hold SNM, while WTP improves by 6.82%. In addition, a supply voltage increment of 25% reduces the Read SNM degradation by 40%, while strengthening the cell pull-down transistors by 1.5× reduces the degradation by only 22%. Moreover, the results reveal that 8T cell degrades 1.31× faster than 6T cell, and that FinFET cells are more vulnerable (∼2×) to BTI degradation than planar CMOS cells.