SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks

This paper presents experimental Single Event Gate Rupture (SEGR) data for Metal-Insulator-Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO
₂
-Si
₃
N
₄
structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross-section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed.