Feasibility Study of ${\rm SrRuO}_{3}/{\rm SrTiO}_{3}/{\rm SrRuO}_{3}$ Thin Film Capacitors in DRAM Applications

In this paper, we have investigated the leakage current versus voltage characteristic of high-k thin film capacitors over a large temperature range. Fabricated samples, consisting of a 10-nm thin SrTiO
₃
(STO) layer as a dielectric material and SrRuO
₃
as electrodes, have been examined. Electrical measurements performed at different temperatures reveal leakage currents that exceed 10
^-7
A/cm
²
at 1 V, a requirement needed for dynamic random access memory (DRAM) applications. We perform a detailed simulation study for the measured samples, making use of a modified drift diffusion model, which also takes into account charge trapping/detrapping effects and nonlocal tunneling. Based on our simulations, we propose an explanation for the large leakage currents observed experimentally. They can be attributed to a trap-assisted tunneling process that is enhanced by oxygen vacancies in the STO dielectric layer. We are thus able to reproduce the temperature and voltage dependence of the measured currents and can use our model to examine the impact of different physical parameters on the behavior of the capacitor structure - a first step toward device optimization. A feasibility analysis is performed for a 1T1C DRAM cell using an optimized deep trench STO capacitor with a reduced oxygen defect density. The simulation results underline the advantages of our modeling procedure using a commercial technology computer aided design (TCAD) framework: once the complex leakage mechanism is implemented, it can be activated on arbitrary 3-D structures, taking advantage of all the postprocessing or visualization capabilities.