A measurement technique for analyzing bitline mode soft errors in half-micron design DRAMs

A technique for analyzing dynamic RAM (DRAM) bitline model errors is presented. Arrayed stripe junctions are fabricated instead of bitlines and the charge collected by each stripe junction when irradiated by alpha -particles is measured. The collection mechanism is clarified and the scaling of collected charges in downscaled DRAMs is estimated, by analyzing the profile of the charge shared by each junction. In the case of folded bitline, charges collected by adjacent bitlines canceled each other because the junctions not hit by alpha -particles also collected charge by diffusion. However, when the junction width is less than 0.6 mu m, the charge collected by diffusion becomes negligible due to the potential barrier caused by channel-cut impurities. For this reason, the use of the folded bitline for cancellation of a alpha -particle induced noise will disappear in megabit DRAMs.<
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