Fault chip defect characterization for wafer scale integration

A fault chip was designed and fabricated on a 2- mu m CMOS wafer-scale integration (WSI) process with greater than 90% wafer coverage. The chip consists of pinhole array capacitors, serpentine resistors, and comb resistors. These structures are tailored to simulate the basic cell in the WSI circuit. Defect cluster analysis, using the negative binomial distribution, indicated that significant clustering occurs for a number of defect types and varies from wafer to wafer.<>