JACS-Pak/sup TM/ flip-chip chip scale package development and characterization

As the drive towards smaller portable communication products continues, conventional, peripheral leaded surface mount packaging technologies are beginning to reach their practical limits. Ongoing technology development and deployment activities in the area of direct chip attach and fine pitch ball grid array packaging have been underway within Motorola for the last decade. More recently, these two core competencies have been effectively leveraged leading to the development of a robust flip chip based Chip Scale Packaging technology dubbed JACS-Pak/sup TM/ CSP. The mix of technological capabilities that enabled this rapid development and qualification are discussed in this paper. To achieve the rapid deployment goal this program has used simulations extensively from the very onset of the program. A detailed cost modeling simulation identified the three major cost contributors to the overall package costs as wafer bumping costs, interposer substrate cost and manufacturing throughput. This focused the development effort on a low cost solution. Nonlinear finite element modeling and simulation was used at every stage of package development for design evaluation, design directions and design space determination. Finite element predictions at component level and board level were validated using micro moire laser interferometry for in-plane deformation measurement and Twyman-Green interferometry for out of plane deformation measurements. A detailed reliability testing program enabled confidence in the package performance and provided validation of the finite element based life time prediction capability.