Design and implementation of a BIST embedded inter-integrated circuit bus protocol over FPGA

The I
²
C (Inter-Integrated Circuit) protocol is used to attach two devices for communicating with each other in a fast way excluding data losses. With the fast development of Integrated Circuits (ICs) technology, the complication of the circuits has also raised. Therefore, the complexity of the circuit requires self-testability in hardware to palliate the product failure. Built-in-self-test (BIST) is such a technique which can meet the necessity of self-testability with an effective solution over pricy circuit testing system. This paper represents designing and implementation of Inter-Integrated Circuit (I
²
C) protocol with self-testing ability. The need of programming for setting up a network with two devices is no longer needed in this proposed system. In order to attain compact, stable and reliable data transmission, the I
²
C is designed with Verilog HDL language and synthesized on Spartan 2 FPGA. An EEPROM and FPGA Spartan 2 are used for the communication testing where the FPGA is master and EEPROM is a Slave.