High resolution failure analysis of silver-sintered contact interfaces for power electronics

In this paper, results of failure analysis on silver-sintered chip backside and substrate contacts for power electronics modules using non-destructive Scanning Acoustic Microscopy (SAM), high resolution Scanning and Transmission Electron Microscopy (SEM, TEM) as well as Time-of-Flight Secondary Ion Mass Spectrometry (ToF SIMS) are presented. Specific attention is given to the microstructure of both contact interfaces, chip metallization to silver-sinter layer and silver-sinter layer to substrate metallization. In general, silver-sinter joints show an excellent bonding quality for most of the investigated chip and substrate metallization systems. Critical failure sites identified in this study are the formation of silver sulfide (Ag2S) at Ag-metallization/ Ag-sinter interfaces and contaminations on top of chip and substrate metallizations. Beside the interface issues, micro cracks and void like defects were detected within some specific chip and substrate metallization systems, respectively. Such defects can affect the strength properties and form a risk for both bonding quality and reliability.