Impact of the control on the size of the output capacitor in the integration of Buck converters

One of the main challenges in PowerSoC converters is the integration of the output capacitor. In some applications, the minimum value of the capacitance is constrained not by the maximum allowed voltage ripple but by dynamic requirements. This paper investigates for a 10 MHz Buck converter if the design of very fast controls can reduce the required output capacitor and which controls are more suitable. It is also analyzed the effect that the moment in which the load transient can occur has on the reduction of the size of the output capacitor.