A proper model for testing the planarity of electrical circuits

The question of whether an electrical circuit can be laid out on a plane, without resorting to crossovers or multilayer wiring, is usually answered by testing the planarity of a graph representing the circuit. Two commonly used representations are shown to be inadequate. We present the following new representation, and show it to be complete and unrestrictive: The graph has one node for each circuit module, and one node for each net; for every net with k modules, there is a “star” of k edges connecting the net's node to each of the modules of the net.