High voltage SOI VLD PMOS with charge-balanced surface super junction layer

A novel high voltage SOI VLD (Variation of Lateral Doping) PMOS, which has a charge-balanced surface super junction (SJ) layer, is proposed. VLD layer yields an enhanced spread of space charge region to sustain the applied high voltage during the forward blocking mode. Charge balance and maximum breakdown voltage (BV) occur when the doping concentration of the p pillars is slightly higher than that of the n pillars. Further reduction of specific on-resistance (R
_{on, sp}
) for a given BV is achieved by utilizing high aspect ratio surface SJ pillars. Simulation results show that the proposed PMOS with L
_d
=35 μm and N
_A
=N
_D
=1E17 cm
^-3
can achieve a BV of 582 V and R
_{on, sp}
of 210 mΩ·cm
²
, leading to a power figure of merit (FOM) of 1.6 MW·cm
^-2
.