19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T
AC
) and low RD-V
DDMIN
, particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high RD-V
DDMIN
and slow T
AC
. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (R
H
/R
L
) between the high-R state (HRS, R
H
) and low-R state (LRS, R
L
). ReRAM also have a high R
L
, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited RD-V
DDMIN
, and slow T
AC
due to high-R
L
and small R-ratio; (2) increase in energy due to large set DC-current (I
DC-SET
) resulting from wide set-time (T
SET
) distribution. This study develops a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-V
DDMIN
and 1.7× faster T
AC
across various V
DD
, compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off I
DC-SET
of faster-T
SET
devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves T
AC
= 404ns at V
DD
= 0.27V and confirms the I
DC-SET
cut-off by SBWT.