Tutorial: Methodology for designing reliable clock networks

This tutorial covers the clock network design methodology, especially focusing on the construction of robust clock under PVT (process-voltage-temperature) variation. First, the basic synthesis flow of clock networks is described with the emphasis of key factors to be considered during the design process. Second, a more in-depth analysis and the related problems caused by the PVT variation are discussed, followed by enumerating the state-of-art design and optimization techniques to address the problems. Thirdly, the diverse structures of clock networks are described, and their pros and cons are summarized with a numeric data extracted from intensive simulation. Finally, the clock design flow is moved to the area of 3D ICs, and what the unique issues to be addressed are and how they are currently solved will be presented.