Implementation of pipelined sobel edge detection algorithm on FPGA for High speed applications

In this paper we present Implementation of pipelined Sobel edge detection algorithm on FPGA for High speed applications. An optimized Gradient-based edge detection method which reduces the delay by around 50% when compared to the standard architecture has been proposed in this paper. The algorithm is implemented on Spartan 3E FPGA board. The Video Graphics Array (VGA) is developed to interface the FPGA to the monitor to display the edge detected image.