Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors

Short-gate length epitaxial Si_1-xGe_x/Si multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of Si_0.7Ge_0.3/Si or Si_0.7Ge_0.3/Si/Si_0.7Ge_0.3/Si shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in Si_0.7Ge_0.3/Si/Si_0.7Ge_0.3/Si core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.