A complete pipelined parallel CORDIC architecture for motion estimation

In this paper, a novel fully pipelined parallel CORDIC architecture is proposed for motion estimation. Unlike other block matching structures, it estimates motion in the discrete cosine transform (DCT) domain instead of the spatial domain. As a result, it achieves high system throughput and low hardware complexity as compared to the conventional motion estimation design in MPEG standards. That makes the proposed architecture very attractive in real-time high-speed video communication. Importantly, the DCT-based nature enables us not only to efficiently combine DCT and motion estimation units into a single component but also to replace all multiply-and-add operations in plane rotation by CORDICs to gain further savings in hardware complexity. Furthermore, this multiplier-free architecture is regular, modular, and has solely local connection suitable for VLSI implementation. The goal of the paper is to provide a solution for MPEG compatible video codec design on a dedicated single chip.