Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (V_ds) and substrate (V_bs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (r_j), and substrate impurity concentration (N_B) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.