Asymmetric Driving Current Modification of CMOS LTPS-TFTs With ${\rm HfO}_{2}$ Gate Dielectric

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO
₂
gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO
₂
/poly-Si interface. P-channel LTPS-TFT has much higher Idrv ~ 0.789 mA than the n-channel LTPS-TFT ~ 0.274 mA under the same overdrive gate voltage. This asymmetric I
_drv
is due to the characteristics of field effect mobility μ
_FE
that p-channel LTPS-TFT has much higher hole μ
_FE
~ 80.16 cm
²
/Vs than the electron μ
_FE
~ 38.26 cm
²
/V s of n-channel LTPS-TFT. The modification of HfO
₂
/poly-Si interface by O
₂
plasma can enhance the electron μFE ~ 34% and reduce the hole μ
_FE
~ 22.4%, resulting in balanced I
_drv
of CMOS LTPS-TFTs that n-channel device shows I
_drv
~ 0.553 mA and p-channel device shows I
_drv
~ 0.590 mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO
₂
gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits.