Design and FPGA implementation of binary squarer using Vedic mathematics

In this paper, a squarer based on Vedic mathematics is proposed. Vedic mathematics is one of the ancient Indian mathematics which contains sixteen sutras. These sutras can be used to solve problems in any branch of Mathematics in a faster way. The proposed squarer is based on sutra called Ekadhikena Purvena. It means that “one more than the previous”. This sutra is used for finding the square of decimal numbers ending with `5'. In this paper this sutra is generalized and used for squaring of binary numbers. The proposed squarer is compared with duplex squarer for 8, 16 and 32-bit cases in Cyclone III FPGA EP3C16F484C6. The proposed squarer saves area by almost 50% and reduces delay by 50% when compared with duplex squarer in 32-bit case.